The logical and electrical behavior of a bridging defect, an unintended electrical connection or “short” between nodes in an integrated circuit (IC) design, has long been a subject of research within the test community. Bridging defects are a prime cause of IC manufacturing yield loss, and reducing their number thus has significant financial benefit for an IC manufacturer. Bridging defects, especially high-resistance bridges, may also escape detection during manufacturing test. An IC with an undetected bridge may thus erroneously be shipped to a customer, where it may fail immediately or after an extended period of use.
In no field is the ability to anticipate and accommodate the varied behaviors of bridging defects more central to success than in fault diagnosis, the goal of which is to determine the physical location of a defect. In light of the complexity and expense of modeling all of the known scenarios and physical factors that affect bridge behavior, much creative work has been done to find ways to diagnose bridging defects using simple logical fault models. The logical behavior caused by a short between two or more nodes, however, depends on such physical details as the relative drive strengths of the transistors driving the bridged nodes, the input logic thresholds of gates downstream of the bridge, and the resistance of the bridge itself. The possibility of a bridge introducing a feedback path into a circuit, or of exhibiting “Byzantine Generals” behavior (in which not all of the logic gates downstream of the defect site interpret the degraded voltage levels on their input as the same logic value) illustrates the difficulty of capturing the complexities of bridging defects with simple logical models. For these reasons, diagnostic methods that rely on logical fault models must tolerate defective circuit behavior that is not anticipated by the models. This tolerance can lead to less precise diagnosis or to diagnosis of the wrong defect.
As an alternative to logical fault models, the quiescent power supply current (IDDQ) bridge fault model has been used to diagnose bridging defects. The IDDQ bridge fault model avoids the problems inherent in predicting the logical behavior of a bridge by ignoring logical behavior entirely. Instead, the model predicts only the circumstances under which an IC, while in a quiescent state, will draw additional current (“defect current”) due to the presence of a bridging defect. For a typical complementary metal oxide semiconductor (CMOS) integrated circuit (IC) in a standby or quiescent state, IDDQ includes mainly leakage/background current. A bridging defect between two nodes may significantly elevate the IDDQ so that the value of the IDDQ may indicate whether a bridging defect exists. Diagnostic methods based on the IDDQ bridge fault model reconcile an observed IDDQ value with the logic states of two nodes to determine whether the two nodes are bridged.
A fundamental issue for diagnostic methods using the IDDQ bridge fault model is the set of candidate bridging faults considered during a diagnosis. Even a relatively small IC containing, e.g., a million circuit nodes has more than half a trillion pairs of nodes, any one of which could in theory be connected by a bridging defect. Consideration of all such pairs of nodes (exhaustive two-node bridge diagnosis) has typically been considered computationally intractable for large industrial designs.
As such, an attribute common to most IDDQ-based bridge diagnostic methods is the reliance on a set of so-called “realistic” bridging faults. A set of realistic bridges is determined prior to a diagnosis by an examination of the physical layout, e.g., layout extraction. The object of the physical examination is to identify pairs of nodes whose physical proximity renders them more likely to be connected by a bridging defect. Layout extraction typically produces a list of candidate bridge faults whose number is a small fraction of all possible two-node bridges. Thus, the consideration of only realistic bridges significantly reduces the CPU resources required for diagnosis.
Unfortunately, at least two factors limit the applicability of any diagnostic method that relies on a set of realistic bridges. First is the expense of extracting and storing the realistic bridges. Layout extraction is typically expensive in terms of CPU resources. This expense is acceptable on a one-time basis for an IC design produced in a high volume, for which one would like to run many diagnoses. However, for an IC manufacturer that fabricates hundreds of different ASIC designs every year, layout extraction clearly becomes an onerous prerequisite for diagnosis.
However, a more significant disadvantage of limiting diagnosis to a set of realistic faults is that the rules used during layout extraction to determine which bridges are “realistic” are based on assumptions that may not always be valid. In order to reduce run time and storage space, for example, a layout extraction will typically identify only bridges between nodes that lie within the same process layer, even though the occurrence of vertical bridges connecting nodes in different process layers is well documented. In general, the capacity of a semiconductor manufacturing line to produce bridging defects that are “unexpected” is significant. The ability to diagnose bridging defects that one does not know in advance to expect is an advantage that cannot be realized by methods that consider only realistic bridges.
Chakravarty and Suresh, IDDQ Measurement Based Diagnosis of Bridging Faults in Full Scan Circuits, 7th International Conference on VLSI Design (January 1994), propose a method for performing exhaustive two-node bridging fault diagnosis using IDDQ. Chakravarty and Suresh rely on an implicit representation of all possible two-node bridges using a “set of ordered pairs of sets (SOPS).” The amount of memory required for this method, however, can increase exponentially and potentially exceed the capacity of a computer as each test vector is considered and each SOPS is subdivided. In addition, results for the Chakravarty and Suresh method were published only for a set of small benchmark circuits, and even these results include a test case that requires almost an hour of CPU time. The application of the Chakravarty and Suresh method is thus not a feasible alternative for even moderately-sized industrial circuits, whose sizes exceed that of the benchmark circuits by 100 times or more.
Based on the above, there is a need in the art for a diagnostic method that can consider bridging defects between all pairs of nodes in an IC chip in an efficient way. The present state of the art technology does not provide a satisfactory solution to this need. The current invention resolves, among others, this problem.